The invention relates to an integrated selection circuit for a number N of potentials Ui . . . , which is integrated in a complementary insulated-gas field-effect transistor technique. Such types of selection circuits are disclosed, for example, in DE-OS No. 26 07 042, FIGS. 2 and 3. These selection circuits are designed for being controlled by a two- or three-bit binary signal and consist of the series arrangements of n-channel or p-channel transistors arranged in parallel with respect to the voltage output, with the number of transistors of the same channel conductivity type per series arrangement corresponding to the number of bits of the binary signal, and with the number of the series arrangements corresponding to the number of states of the binary signal. Thus, the aforementioned FIG. 2, shows an arrangement for a two-bit binary signal comprising accordingly 2.sup.2 =4 series arrangements, and per series arrangement two n-channel or two p-channel transistors. The aforementioned FIG. 3 shows with respect to a three-bit binary signal, an arrangement including 2.sup.3 =8 series arrangements and, per series arrangement three p-channel or three n-channel transistors.
The number N of potentials capable of being connected by the conventional arrangements, is identical to the number of states of the binary signal with half the number of potentials (N/2) which are within the negative half of the range of operating voltage, being connected to the series arrangements of n-channel transistors while the other (more positive) half is connected to the p-channel series arrangements. Accordingly, with the arrangement as shown in FIG. 2, a total of four potentials and, with the arrangement as shown in FIG. 3, a total of eight potentials can be connected through. The gates of the individual transistors are selected with the aid of the individual bits either directly or via interconnected inverters, with no mention being made, however, about the concrete realization thereof in terms of the employed circuit technique.
The prior art arrangements, however, have to pay for the advantages of a low power draw and a small number of transistors by the disadvantage of a higher output resistance of the respective through-connected potential. This higher output resistance results on account of the series arrangement of more than one transistor in cases where the channel widths of the transistors and, consequently, their surface requirement is not increased in proportion to the number of transistors per series arrangement. This measure, however, (and especially in the case of a large N) the advantage of the small number of transistors would be lost again.